(1) Field of the Invention
The invention relates to a method of connecting three-dimensional integrated circuits chips, and more particularly, to a method of connecting integrated circuit chips using a trench method.
(2) Description of the Prior Art
The density and scale of integration of integrated circuit chips will continue to increase in the future. High density integrated circuits have a limited space available without shrinking transistor device sizes. One of the technologies which provide a means to break through the space limitation is a three-dimensional integrated circuit technology.
Using three-dimensional integrated circuit technology, high density integrated circuits can be produced which consist of one master chip and some subordinate chips. All control circuits can be put in the master chip and other function block circuits can be arranged in subordinate chips with interconnection between the chips. For example, in a Read-Only Memory (ROM) or Static Random Access Memory (SRAM) circuit, the control circuit can be fabricated on the master chip and 8 input/output (I/O) blocks can be formed in each subordinate chip. The chips can be stacked by interconnection through the pad window. The interconnection between chips can be fabricated during integrated circuit processing. Using this method, we can fabricate a high density ROM or SRAM stack memory chip.
U.S. Pat. No. 4,818,728 to Rai et al teaches a chip interconnection method involving metal studs on a surface of one chip and solder deposits on the surface of the second chip. The solder deposits are melted and the chips connected by fixing the metal studs into the melted solder. U.S. Pat. No. 4,998,665 to Hayashi teaches a chip interconnection method in which a high melting point conductive material projection is plunged into a liquid low melting point conductive material and then cooled to complete the connection.